m monad-knowledge FIIT STU · open research vault
hardwar

raspberry-pi-5

Also known as: Raspberry Pi 5, RPi 5, Pi 5

Description

The Raspberry Pi 5 is the first Pi with native PCIe (single-lane gen 2/3), which is what makes the Pi 5 + M.2 HAT + AX210 sensing stack possible. Important — Pi 5 is not a Nexmon CSI target: its on-board Wi-Fi chip (Broadcom BCM4378 / CYW43xxx successor) is not in the Nexmon-supported list and has no published CSI patch.

The Pi 5's role in this lab is the Linux CSI host carrying AX210 over PCIe — i.e. a small headless Linux machine running feitcsi (or PicoScenes), not a Nexmon CSI sniffer. 14× units in the lab, each paired with an M.2 HAT + AX210 (also 14× each).

This entry supersedes the Pi-3B+/4 framing in raspberry-pi for the active deployment; the older entry stays as a historical reference for the Nexmon literature.

Specs / capabilities

  • Quad-core ARM Cortex-A76 @ 2.4 GHz, 4 / 8 GB LPDDR4X
  • PCIe 2.0 ×1 (gen 3 with dtparam=pciex1_gen=3 overlay) — the load-bearing feature
  • On-board Wi-Fi (BCM4378) — no CSI; treat as control / SSH plane only
  • 2× USB 3.0, 2× USB 2.0, Gigabit Ethernet
  • 5 V / 5 A USB-C power; active cooler recommended for sustained CSI capture

CSI extraction path

The Pi 5 + M.2 HAT + AX210 stack lets the AX210 NIC sit on a real PCIe lane (not USB), which is what FeitCSI / PicoScenes expect. Capture pipeline:

AX210 (M.2 carrier via Pi M.2 HAT) ──PCIe──> Pi 5 (Linux, FeitCSI patched iwlwifi)
                                                    │
                                                    └──> CSI dump file / TCP stream

The Pi 5 holds the FeitCSI kernel modules and a thin userspace collector that timestamps + forwards CSI frames over TCP to a collection host. 14 nodes ⇒ 7 TX/RX pairs OR 14 RX-only nodes for multi-link MIMO-grade coverage.

Role in the experiment series

  • EXP-P1: PCIe link sanity (Gen 2 vs Gen 3 overlay, link width); FeitCSI driver build; per-node CSI capture rate validation; NTP / PTP sync across 14 nodes.
  • EXP-F1: 4 nodes (2 TX/RX pairs) in the EXP-F1 meeting room.
  • EXP-F2: same 4 nodes, fixed for 30 days, drift study.
  • EXP-F3: scale to 8 nodes across two rooms for the cross-geometry transfer.

Quirks / known issues

  • Not a Nexmon target. Don't try to repurpose the on-board chip.
  • PCIe gen 3 is officially unsupported but typically stable with the dtparam=pciex1_gen=3 overlay; cap at gen 2 for production if any link instability appears.
  • Active cooling required for sustained 100 % CPU + AX210 traffic — the passive case will throttle.
  • The M.2 HAT uses a 16-pin ribbon FFC for the PCIe link; ribbon damage from frequent reseating is the most common bring-up failure.
  • AX210 firmware version + Linux kernel + FeitCSI must align — see feitcsi for the working matrix.

Tooling

  • Raspberry Pi OS 64-bit (Bookworm or newer)
  • FeitCSI patched iwlwifi (preferred, free + open-source)
  • PicoScenes (alternative, paid, supports more parsers)
  • iperf3 for the Layer-P throughput sanity
  • chrony or ptpd for sub-ms time sync across nodes

Used by (papers)

  • Pi 5 + AX210 + FeitCSI is a 2024+ stack; no large paper corpus yet. Closest published reference for the AX200/AX210 + FeitCSI side is guarino2026_e72c ↗.
  • raspberry-pi — Pi 3B+/4 + Nexmon lineage (historical; do not use for Pi 5 deployments)
  • pi-m2-hat — the PCIe carrier
  • intel-ax210 — the NIC
  • feitcsi — the CSI extraction toolchain (creates note in _knowledge/methods/ if not present)