m monad-knowledge FIIT STU · open research vault
hardwar

esp32-s3

Also known as: ESP32-S3, ESP32-S3-DevKitC-1, Espressif ESP32-S3

Description

ESP32-S3 is the dual-core Xtensa LX7 with USB-OTG, 8 MB PSRAM-capable, BLE 5.0, and Wi-Fi 4 (802.11n). Compared to the RISC-V C5/C6, the S3 trades Wi-Fi 6 capability for an extra core, PSRAM, and far more peripherals. In this lab the S3 is not the CSI extractor — it is the high-throughput logger sidecar for esp32-c5, because the SDMMC 4-bit mode at 40 MHz to a UHS-I A1/A2 microSD delivers 10–20 MB/s sustained, which is the throughput class C5 CSI streams need at 80 MHz × 100 Hz packet rate.

5× units in the lab — fewer than C5/C6 because each S3 pairs with two C5 nodes (one per TX/RX direction); not every C5 needs a sidecar.

Specs / capabilities

  • Dual-core Xtensa LX7 @ 240 MHz, 512 KB SRAM, up to 8 MB PSRAM
  • Wi-Fi 4 (802.11n) 2.4 GHz only, 20 / 40 MHz channels — no Wi-Fi 6, no CSI on the modern chassis
  • Bluetooth 5.0 LE (advertising + scanning + connections)
  • USB-OTG (full-speed), SDMMC 4-bit @ 40 MHz, SPI / I²C / UART
  • < $5 module, ~$10 DevKitC-1
  • ESP32-S3-DevKitC-1-N32R16V variant ships 32 Mbit flash + 16 Mbit PSRAM (used in the sidecar build)

Role in the experiment series

Primary role — SD-logger sidecar. Producer ISR receives CSI binary frames from a paired C5 over SPI (master = C5, slave = S3) or high-speed UART (3 Mbaud framed binary + CRC). Ring buffer in PSRAM. Consumer FreeRTOS task pulls 64 KB blocks and appends to a FAT32 / exFAT log file on UHS-I SDXC. Target sustained throughput 10–20 MB/s; see esp32-c5-s3-sidecar for the wiring and back-pressure protocol.

Secondary role — mobile-app-facing companion. S3's USB-OTG + BLE 5.0 + Wi-Fi 4 make it a serviceable bench-side endpoint for the mobile app when the C5/C6 are busy on CSI duty.

Quirks / known issues

  • Not a Wi-Fi 6 / 5 GHz / CSI device. Don't try to make it one — use C5 instead.
  • SDMMC requires short SD-socket wires for signal integrity; keep CLK / CMD / D0–D3 parallel and < 5 cm where possible.
  • N32R16V variants ship with PSRAM enabled in eFuse; older N8 variants don't.
  • USB-OTG and the JTAG/Serial both want the USB pins — pick one per build.

Tooling

  • ESP-IDF ≥ v5.1
  • esp_vfs_fat_sdmmc_mount for the SDMMC mount
  • driver/sdmmc_host.h for the 4-bit-mode config
  • esptool.py for flashing

Used by (papers)

  • General ESP32 CSI literature (choi2022_17c2 ↗, koo2026_a08d ↗) — but specifically about the ESP32 / S2 / S3 family as a sensing chassis, not as a logger.
  • esp32-c5 — the CSI extractor S3 logs for
  • esp32-c6 — BLE / 2.4 GHz Wi-Fi 6 sibling
  • esp32-c5-s3-sidecar — dual-board recipe combining the two
  • esp32 — generic family baseline