m monad-knowledge FIIT STU · open research vault
hardwar

esp32-c5

Also known as: ESP32-C5, ESP32-C5-DevKitC-1, Espressif ESP32-C5

Description

Espressif's first dual-band Wi-Fi 6 RISC-V SoC. C5 sits between esp32-c6 (Wi-Fi 6 2.4 GHz only + 802.15.4) and a full Linux host: it can act as both an 802.11ax station/AP and a CSI-extracting monitor on 2.4 GHz and 5 GHz at 20 MHz / 40 MHz / 80 MHz channel widths. 10× units in the lab — the largest single sub-population — earmarked as the headline CSI-extraction nodes for the field experiments where a full Pi 5 + AX210 stack is overkill or non-deployable.

Specs / capabilities

  • Single-core 32-bit RISC-V @ 240 MHz, 400 KB SRAM, optional PSRAM
  • Wi-Fi 6 (802.11ax) dual-band: 2.4 GHz and 5 GHz, 20 / 40 / 80 MHz channels
  • Bluetooth 5.0 LE (advertising + scanning + connections)
  • 802.15.4 (Thread / Zigbee / Matter) — same radio block as C6
  • USB-Serial-JTAG, SPI / I²C / UART / SDMMC peripherals
  • < $10 module-class, ~$15 DevKitC-1 board
  • ESP32-C5-DevKitC-1 reference board ships with on-board antenna + U.FL switch

CSI extraction path

Two routes:

  1. Built-in esp_wifi_set_csi_rx_cb() API (ESP-IDF ≥ v5.4) — capture HE-LTF CSI for both 2.4 GHz and 5 GHz frames received in promiscuous / connected mode. Subcarrier count scales with channel width: ~256 sub-carriers at 80 MHz on 5 GHz.
  2. Streaming sidecar — pack CSI snapshots as compact binary frames, hand off over SPI / high-speed UART to an esp32-s3 SD-logger sidecar when the host can't sink the rate. See esp32-c5-s3-sidecar for the dual-board recipe.

The 5 GHz Wi-Fi 6 path is what choi2022_17c2 ↗ and the ESP32 CSI-Tool lineage couldn't do — C5 is the cheapest way to get 5 GHz HE-LTF CSI without a Linux NIC.

Role in the experiment series

  • EXP-P1 (platform bring-up): per-chip CSI capture sanity; throughput vs channel-width sweep; SPI/UART handoff to S3.
  • EXP-F1 / F2 / F3 (field): deployed as 2 TX/RX pairs per room in the diagonal + horizontal link geometry inherited from choi2022_17c2 ↗ Wi-CaL.

Quirks / known issues

  • C5 is new (2025 silicon ramp). Some early DevKitC-1 boards ship with an older bootloader that the v5.4 toolchain refuses; flash the latest bootloader first.
  • 5 GHz CSI requires a regulatory-domain-set country code before the radio will tune the higher bands. Set CONFIG_ESP_WIFI_REGD in sdkconfig or via runtime API.
  • Single-antenna part — no MIMO. For multi-antenna CSI use the Pi 5 + AX210 stack.

Tooling

  • ESP-IDF ≥ v5.4 (master is faster but unstable)
  • esp_wifi_set_csi_rx_cb() for the CSI callback hook
  • csikit / custom Python collectors for offline analysis
  • esptool.py for flashing

Used by (papers)

  • The ESP32 CSI-extraction lineage (choi2022_17c2, koo2026_a08d) covers the original ESP32 / ESP8266 chips; no published paper yet uses the C5 specifically because it is new silicon. This lab's deployment is among the first.
  • esp32-c6 — 2.4 GHz Wi-Fi 6 sibling with 802.15.4
  • esp32-s3 — high-throughput SD-logger sidecar
  • esp32-c5-s3-sidecar — dual-board recipe pairing C5 + S3
  • esp32 — generic family baseline
  • raspberry-pi-5 — when ESP32-class CSI isn't enough